Digital prototype of LLRF system for SSRF

This paper describes a field programming gate array(FPGA)based low level radio frequency (LLRF)prototype for the SSRF storage ring RF system.This prototype includes the local oscillator(LO),analog front end,digital front end,RF out,clock distributing,digital signal processing and communication functions.All feedback algorithms are performed in FPGA.The long term of the test prototype with high power shows that the variations of the RF amplitude and the phase in the accelerating cavity are less than 1%and 1°respectively.and the variation of the cavity resonance frequency is controlled within ±10 Hz.

作 者： ZHAO Yu-Bin YIN Cheng-Ke ZHANG Tong-Xuan FU Ze-Chuan ZHAO Zhen-Tang DAI Zhi-Min LIU Jian-Fei WANG Fang   作者單位： ZHAO Yu-Bin,YIN Cheng-Ke,ZHANG Tong-Xuan,FU Ze-Chuan(Shanghai Institute of Applied Physics,CAS,Shanghai 201800,China;Graduate University of Chinese Academy of Sciences,Beijing 100049,China)

ZHAO Zhen-Tang,DAI Zhi-Min,LIU Jian-Fei,WANG Fang(Shanghai Institute of Applied Physics,CAS,Shanghai 201800,China) 

刊 名： 中國物理C（英文版）  ISTIC 英文刊名： CHINESE PHYSICS　C  年，卷(期)： 2008 32(9)  分類號： O4  關鍵詞： LLRF controller   field programming gate array   feedback algorithm   clock distribution   local oscillator  

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